1. Field of the Invention
The present invention relates to a sound generator, and in particular to an improved sound generator capable of reducing power consumption and improving DRAM download speed by using dedicated DRAM download logic.
2. Description of the Background Art
Nowadays, electronic instruments are pacing a new music field due to their various sound creation capabilities and other functions, in accordance with the rapid development of the computer industry. However, the arrival of the multimedia era requires more effective sound systems for aural satisfaction as well as visual satisfaction. Accordingly, the importance of and demand for more effective sound systems has been increased.
Sound generators are leading components of sound systems, that is, sound generators serve as integrated circuits (ICs) for generating more and better sound.
Currently, as a sound generating method, a frequency modulation (FM) method and pulse code modulation (PCM) are mainly applied to the electronic instruments of analog and digital types.
The FM method obtains a dynamic sound spectrum by using FM in an audio frequency band, and synthesizes natural sounds by similarly reproducing a dynamic spectrum.
The PCM method stores analog waves of the sounds in a memory as a digital sign type after sampling, multiplies the data stored in the memory by an amplitude value, and outputs a resultant value through a D/A converter. The PCM method is carried out simply, and performs as much sampling and storing of sound as possible, if there is enough capacity, thus it is capable of producing sound which is similar to the original sound.
However, most sampling synthesizing methods do not perform sampling of every sound of an instrument, but divides the entire spectrum of sounds into several groups, and samples and stores a representative sound from each group, then obtains the remaining sounds from the representative sound of each group.
FIG. 1 illustrates a conventional sound generator.
As shown therein a CPU interface and clock generating unit 10, which takes charge of a central processing unit (CPU), and an interface, synchronizes a signal received from the CPU with a main clock of the sound generator, and supplies a clock signal necessary for an internal operation by storing instructions of the CPU.
An operation code memory 11 generates an operation code (OC) which is needed for the operation of the sound generator in accordance with an operation signal (OS) outputted from the CPU interface and clock generating unit 10, and a memory controlling unit 12 outputs an address (ADR) of a parameter, necessary for processing each signal, in accordance with the operation code outputted from the operation code memory 11.
A data memory 13 stores the parameter which is needed for processing each signal, such as a filter coefficient, an envelope index number, and algorithm information, etc., and a signal processing unit 14 receives the operation code outputted from the operation code memory 11 and performs a signal processing in accordance with a parameter outputted from the data memory 13.
A signal processing unit 14 generates a desired sound by processing a sampled soundness source received from an external ROM by repetition of adding, subtracting, and multiplying according to an algorithm.
An external memory address generating unit 15 generates an address of an external memory, which stores sound data, in accordance with the operation code outputted from the operation code memory 11.
Now, an operation of the conventional sound generator will be described in detail with reference to the accompanying drawing.
The CPU interface and clock generating unit 10 synchronizes the signal received from the CPU with the main clock of the sound generator, and stores the instruction of the CPU, and supplies a clock signal necessary for the internal operation.
First, when a parameter writing signal WR from the CPU (not shown) is inputted, the CPU interface and clock generating unit 10 controls the memory controlling unit 12 by generating a clock signal (CLK) necessary for the internal operation, thus a parameter needed for processing each signal can be stored in the data memory 13 in accordance with an address outputted from the memory controlling unit 12.
Next, when the operation for storing the parameter is completed, and when an operating signal is outputted from the CPU interface and clock generating unit 10 in accordance with a parameter reading signal RD, the operation code memory 11 generates the operation code necessary for the operation of the sound generator, and repeats an operation of reading/processing a parameter which is needed for signal processing by generating the operation code necessary for the operation of the sound generator.
That is, when the memory controlling unit 12 outputs an address signal of the parameter stored in the data memory 13 in accordance with the operation code outputted from the operation code memory 11, the data memory 13 outputs a parameter which corresponds to the address signal to the signal processing unit 14. The external memory address generating unit 15 accesses the external ROM (not shown) by generating address signals (RA{overscore (S, CA)}S, {overscore (ROM)}EN, RAMEN, ADDR) in accordance with the operation code outputted from the operation code memory 11.
As a result, the signal processing unit 14 synchronizes the operation code outputted from the operation code memory 11 with an operating signal, and repeatedly performs the addition, subtraction, and multiplication of the sampled sound sources outputted from the external ROM in accordance with the parameter outputted from the data memory 13, for example the algorithm, thereby processing the sampled sound sources received from the external ROM and generating the desired sound. Here, the parameter includes information necessary for processing the signal, such as the filter coefficient, the envelope index number, etc.
In case of downloading sound data retained by a user to a DRAM, the conventional sound generator should repeatedly read a predetermined portion of the operation code memory 11 until all of the sound data is written in the DRAM. Here, an operation code with respect to data writing (instead of sound generation) is written, thus when restarting the sound generation, a new parameter should be rewritten. This is time consuming and complicated.
Accordingly, an interval for reading a predetermined portion of the operation code memory 11 is determined by an interval for generating 1 to 2 voices. In this case, it takes 45 seconds to write data of 4M, so that it is too slow for a user to use.
In addition, the CPU interface and clock generating unit 10 of the conventional sound generator unconditionally outputs data received from the CPU. Therefore, the CPU interface and clock generating unit 10 is not able to check whether the data memory 13 is ready for receiving the data or not, and thus a case of losing the data arises.
Also, the memory continuously generates a clock signal having the same speed as the operation clock of the sound generator although it is in an idle mode, thus resulting in problems, such as unnecessary power consumption and instability of data.
Accordingly, it is an object of the present invention to provide a sound generator capable of increasing a DRAM download speed and reducing power consumption by using a dedicated DRAM download logic.
To achieve the above objects, there is provided a sound generator which includes a DRAM download control unit for downloading data to a DRAM at high speed in accordance with a DRAM download signal outputted from a central processing unit (CPU).
The DRAM download control unit includes: a signal synchronizing and interface unit for generating a clock signal in accordance with a DRAM download start signal so that a download is enabled at a point in time which 32 voices representing each group are completed; a download signal generating unit for generating a download signal in accordance with a clock signal outputted from the signal synchronizing and interface unit; a refresh signal generating unit for generating a refresh clock signal to prevent downloaded data from being lost when the DRAM download has been completed; a download address and data unit for receiving address and data signals from the signal synchronizing and interface unit and outputting the address and data signals when downloading data; a state display unit for informing the CPU whether it is appropriate to write the data to the DRAM; and a selecting unit for selectively outputting signals, which are outputted from the download signal generating unit, the refresh signal generating unit, and the download address and data unit, in accordance with an external selecting signal.
Additional advantages, objects and features of the invention will become more apparent from the description which follows: